Reconfigurable Hardened Latch and Flip-Flop for FPGAs
| Autor: | Hamzeh Ahangari, Smail Niar, Ozcan Ozturk, Ihsen Alouani |
|---|---|
| Přispěvatelé: | Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201 (LAMIH), Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Centre National de la Recherche Scientifique (CNRS)-INSA Institut National des Sciences Appliquées Hauts-de-France (INSA Hauts-De-France) |
| Jazyk: | angličtina |
| Rok vydání: | 2017 |
| Předmět: |
Triple modular redundancy
Engineering Logic block Field programmable gate arrays (FPGA) 02 engineering and technology Single event upsets Hardware_PERFORMANCEANDRELIABILITY VLSI circuits 01 natural sciences law.invention MBus law 0202 electrical engineering electronic engineering information engineering Reconfigurability Hardware_ARITHMETICANDLOGICSTRUCTURES FPGA Computer control systems Flip-flop Sstatic latch Integrated circuit reliability Economic and social effects Three orders of magnitude Reconfigurable structure Latches Reliability Reconfigurable computing Reconfigurable hardware 020202 computer hardware & architecture Single event upset Static latch Transistors 0103 physical sciences Radiation hardening (electronics) Multiple bit upset [INFO]Computer Science [cs] Field-programmable gate array 010308 nuclear & particles physics business.industry SRAM cells Field programmable gate arrays Radiation hardening Fault tolerant computer systems Reconfigurable devices Embedded system Hardening business Hardware_LOGICDESIGN |
| Zdroj: | 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Jul 2017, Bochum, Germany. pp.433-438, ⟨10.1109/ISVLSI.2017.82⟩ Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, 2017 ISVLSI |
| DOI: | 10.1109/ISVLSI.2017.82⟩ |
| Popis: | Conference name: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2017 Date of Conference: 3-5 July 2017 In this paper, we propose Joint Latch (JLatch) and Joint Flip-Flop (JFF), two novel reconfigurable structures which bring the reconfigurability of reliability to user latches and flip-flops (FFs) in reconfigurable devices such as FPGAs. Specifically, we implement two reconfigurable storage elements that exploit a trade-off between reliability and amount of available resources. In fault prone conditions, JLatch (or JFF) is configured in such a way that four pre-selected normal static latches (or FFs) are combined together at circuit level to form one hardened storage cell. Solution focuses on transient faults such as soft errors, where we show that critical charge is increased by at least three orders of magnitude (1000X) to practically bring immunity against any Single Event Upset (SEU). If four latches inside an FPGA logic block are far enough, it can effectively cope with Multiple Bit Upsets (MBUs) as well. Additionally, provided that special transistor sizing is applied (only necessary for some latch structures), JLatch and JFF take advantage of a novel self-correcting technique to correct any single fault immediately. Our solution provides reconfigurability of reliability with negligible performance and area overhead with only one (two) extra transistor(s) per latch (FF). The delay of this technique is less than the delay of conventional TMR (Triple Modular Redundancy) technique with a majority voter at output. © 2017 IEEE. |
| Databáze: | OpenAIRE |
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