Impact of CMOS post nitridation annealing on reliability of 40nm 512kB embedded Flash array
| Autor: | Thibault Kempf, Jean-Michel Portal, Franck Julien, Arnaud Regnier, Francois Maugain, Stephan Niel, M. Mantelli, Pascal Masson, Jean-Michel Moragues, Marjorie Hesse, Vincenzo Della Marca |
|---|---|
| Přispěvatelé: | Laboratoire de Polytech Nice-Sophia (Polytech'Lab), Université Nice Sophia Antipolis (... - 2019) (UNS), COMUE Université Côte d'Azur (2015-2019) (COMUE UCA)-COMUE Université Côte d'Azur (2015-2019) (COMUE UCA)-Université Côte d'Azur (UCA), Institut des Matériaux, de Microélectronique et des Nanosciences de Provence (IM2NP), Université de Toulon (UTLN)-Centre National de la Recherche Scientifique (CNRS)-Aix Marseille Université (AMU), STMicroelectronics [Rousset] (ST-ROUSSET), STMicroelectronics [Crolles] (ST-CROLLES), Université Nice Sophia Antipolis (1965 - 2019) (UNS), Aix Marseille Université (AMU)-Université de Toulon (UTLN)-Centre National de la Recherche Scientifique (CNRS) |
| Rok vydání: | 2017 |
| Předmět: |
010302 applied physics
Materials science Annealing (metallurgy) business.industry 020208 electrical & electronic engineering Oxide 02 engineering and technology Chip 01 natural sciences Temperature measurement Memory array Threshold voltage chemistry.chemical_compound CMOS chemistry 13. Climate action 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Optoelectronics SILC [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics business ComputingMilieux_MISCELLANEOUS |
| Zdroj: | 2017 IEEE International Integrated Reliability Workshop (IIRW) 2017 IEEE International Integrated Reliability Workshop (IIRW), Oct 2017, Fallen Leaf Lake, CA, United States |
| DOI: | 10.1109/iirw.2017.8361234 |
| Popis: | The impact of CMOS post nitridation annealing (PNA) temperature on a 40nm embedded Flash reliability is studied. Electrical characterizations of the Flash tunnel oxide are carried out on single cell. These are used to explain the better results in terms of endurance and data retention obtained on a 512kB test chip with a lower annealing temperature. This result can be linked with the decrease of nitrogen in the bulk oxide, improving oxide wear out performance against electrical stress and stress induced leakage current (SILC). The on-chip characterization is, here, an invaluable tool to show the extrinsic behavior in the memory array and apply product-like stress. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|