An Efficient Heuristic for Peak Capture Power Minimization During Scan-Based Test
| Autor: | A. Satya Trinadh, Seetal Potluri, Ch. Sobhan Babu, V. Kamakoti |
|---|---|
| Rok vydání: | 2013 |
| Předmět: |
Mathematical optimization
Design for testability Computer science Heuristic (computer science) Peak Capture-Power Power minimization Travelling salesman problem Upper and lower bounds Bottleneck Power (physics) Bottleneck Biconnected Spanning Sub-Graph Problem (BBSSP) Electrical engineering Path problems Power electronics Path (graph theory) Binary search Scan-based testing Test vector ordering Electrical and Electronic Engineering Electronic circuit |
| Zdroj: | Journal of Low Power Electronics. 9:264-274 |
| ISSN: | 1546-1998 |
| DOI: | 10.1166/jolpe.2013.1255 |
| Popis: | IR-Drop induced timing failures during testing can be avoided by minimizing the peak capturepower. This paper models the Capture-Power minimization problem as an instance of the Bottleneck Traveling Salesman Path Problem (BTSPP). The solution for the BTSPP implies an ordering on the input test vectors, which when followed during testing minimizes the Peak Capture-Power. The paper also presents a methodology for estimating a lower bound on the peak capture-power. Applying the proposed technique on ITC'99 benchmarks yielded optimal (equal to the estimated lower bound) results for all circuits. Interestingly, the technique also significantly reduced the average power consumed during testing when compared with commercial state-of-the-art tools. Copyright � 2013 American Scientific Publishers All rights reserved. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|