Scaling of graphene integrated circuits
| Autor: | Enrique A. Carrion, Laura Polloni, Marco Fiocco, Eric Pop, Ruggero Alberti, Roman Sordan, Erica Guerriero, Ashkan Behnam, Massimiliano Bianchi |
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| Rok vydání: | 2015 |
| Předmět: |
Materials science
Graphene Oscillation business.industry Transistor Nanotechnology Hardware_PERFORMANCEANDRELIABILITY Integrated circuit law.invention law Limit (music) Hardware_INTEGRATEDCIRCUITS Optoelectronics General Materials Science Materials Science (all) Electronics business Performance metric Scaling Hardware_LOGICDESIGN |
| Zdroj: | Nanoscale. 7:8076-8083 |
| ISSN: | 2040-3372 2040-3364 |
| DOI: | 10.1039/c5nr01126d |
| Popis: | The influence of transistor size reduction (scaling) on the speed of realistic multi-stage integrated circuits (ICs) represents the main performance metric of a given transistor technology. Despite extensive interest in graphene electronics, scaling efforts have so far focused on individual transistors rather than multi-stage ICs. Here we study the scaling of graphene ICs based on transistors from 3.3 to 0.5 μm gate lengths and with different channel widths, access lengths, and lead thicknesses. The shortest gate delay of 31 ps per stage was obtained in sub-micron graphene ROs oscillating at 4.3 GHz, which is the highest oscillation frequency obtained in any strictly low-dimensional material to date. We also derived the fundamental Johnson limit, showing that scaled graphene ICs could be used at high frequencies in applications with small voltage swing. |
| Databáze: | OpenAIRE |
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