Efficiency analysis of modern vector architectures: vector ALU sizes, core counts and clock frequencies
| Autor: | Adrian Barredo, Marc Casas, Mateo Valero, Juan M. Cebrian, Miquel Moreto |
|---|---|
| Přispěvatelé: | Universitat Politècnica de Catalunya. Doctorat en Arquitectura de Computadors, Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, Barcelona Supercomputing Center, Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
| Rok vydání: | 2019 |
| Předmět: |
Circuits lògics
020203 distributed computing Computer science Càlcul intensiu (Informàtica) -- Consum d'energia Pipeline (computing) Fetch Control reconfiguration Efficiency 02 engineering and technology Parallel computing High performance computing -- Energy consumption Theoretical Computer Science Power wall Hardware and Architecture Vectorization (mathematics) 0202 electrical engineering electronic engineering information engineering Parallelism (grammar) Vector DVFS Informàtica::Arquitectura de computadors [Àrees temàtiques de la UPC] Software Logic circuits Information Systems |
| Zdroj: | UPCommons. Portal del coneixement obert de la UPC Universitat Politècnica de Catalunya (UPC) |
| ISSN: | 1573-0484 0920-8542 2012-1504 |
| DOI: | 10.1007/s11227-019-02841-6 |
| Popis: | Moore’s Law predicted that the number of transistors on a chip would double approximately every 2 years. However, this trend is arriving at an impasse. Optimizing the usage of the available transistors within the thermal dissipation capabilities of the packaging is a pending topic. Multi-core processors exploit coarse-grain parallelism to improve energy efficiency. Vectorization allows developers to exploit data-level parallelism, operating on several elements per instruction and thus, reducing the pressure to the fetch and decode pipeline stages. In this paper, we perform an analysis of different resource optimization strategies for vector architectures. In particular, we expose the need to break down voltage and frequency domains for LLC, ALUs and vector ALUs if we aim to optimize the energy efficiency and performance of our system. We also show the need for a dynamic reconfiguration strategy that adapts vector register length at runtime. Funding was provided by RoMoL ERC Advanced Grant (Grant No. GA 321253), Juan de la Cierva (Grant No. JCI-2012-15047), Marie Curie (Grant No. 2013 BP_B 00243). |
| Databáze: | OpenAIRE |
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