A 40-nm 256-Kb Half-Select Resilient 8T SRAM with Sequential Writing Technique
| Autor: | Toshikazu Suzuki, Shusuke Yoshimoto, Shinji Miyano, Masahiko Yoshimoto, Shunsuke Okumura, Masaharu Terada, Hiroshi Kawaguchi |
|---|---|
| Jazyk: | angličtina |
| Rok vydání: | 2012 |
| Předmět: |
Hardware_MEMORYSTRUCTURES
Generator (computer programming) Computer science business.industry Hardware_PERFORMANCEANDRELIABILITY Static random-access memory Leakage power Electrical and Electronic Engineering Condensed Matter Physics business Cmos process Computer hardware Electronic Optical and Magnetic Materials |
| Zdroj: | IEICE Electronics Express. 9(12):1023-1029 |
| ISSN: | 1349-2543 |
| Popis: | This paper introduces a novel half-select resilient dual write wordline 8T (DW8T) SRAM with a sequential writing technique. The dual write wordlines are sequentially activated in a write cycle, and its combination with the half-VDD precharge suppresses the half-select problem. We implemented a 256-Kb DW8T SRAM and a half-VDD generator with a 40-nm CMOS process. The measurement results of the seven samples show that the proposed DW8T SRAM achieves a VDDmin of 600mV and improves the average VDDmin by 367mV compared to the conventional 8T SRAM. The measured leakage power can be reduced by 25%. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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