Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology
| Autor: | Philippe Roche, Cyril Bottoni, Lorenzo Ciampolini, David Meyer, Patrick Girard, Arnaud Virazel, F. Giner, Sylvain Clerc, Alberto Bosio, Fady Abouzeid, Darayus Adil Patel, S. Naudet, Robin Wilson, J. M. Daveau |
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| Přispěvatelé: | STMicroelectronics, Conception et Test de Systèmes MICroélectroniques (SysMIC), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), University of Virginia [Charlottesville], Computer Science Department, University of Warwick [Coventry] |
| Jazyk: | angličtina |
| Rok vydání: | 2015 |
| Předmět: |
Engineering
SPARC V8 microprocessor Standards microprocessor chips Silicon on insulator Transistors storage capacity 8 Kbit law.invention Low voltage ULV law Hardware_INTEGRATEDCIRCUITS wafer-level tests FDSOI technology Static random-access memory [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics ultralow voltage Microprocessors Energy efficient Cache cache storage business.industry Transistor size 28 nm Electrical engineering SRAM cache Registers RISC CMOS integrated circuits FDSOI Power (physics) silicon-on-insulator Microprocessor CMOS low energy operation Embedded system storage capacity 32 bit fully depleted silicon on insulator technology SRAM chips Cache business |
| Zdroj: | Quality Electronic Design (ISQED), 2015 16th International Symposium on ISQED: International Symposium on Quality Electronic Design ISQED: International Symposium on Quality Electronic Design, Apr 2015, Santa Clara, United States. pp.366-370, ⟨10.1109/ISQED.2015.7085453⟩ ISQED |
| DOI: | 10.1109/ISQED.2015.7085453⟩ |
| Popis: | International audience; This work presents a single-supply SPARC 32b V8 microprocessor designed with Ultra Low Voltage (ULV) adapted standard cells and memories, aiming at low energy operation and stand by power. The microprocessor, equipped with 10 Transistors ULV bitcell 8KB SRAM cache, has been fabricated in Fully Depleted Silicon On Insulator (FDSOI) 28nm technology. A comparative analysis with similar implementations has been provided highlighting the performance gain and power savings that are achieved by our design methodology and implementation technology. Wafer-level tests showed that our ULV adapted microprocessor has an operating range that is functional down to 0.33V and that the ULV able cache can save from 30% to 62% energy. |
| Databáze: | OpenAIRE |
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