A new countermeasure against side-channel attacks based on hardware-software co-design
| Autor: | Enrique Canto-Navarro, Mariano Lopez-Garcia, Ruben Lumbiarres-Lopez |
|---|---|
| Přispěvatelé: | Universitat Politècnica de Catalunya. Departament d'Enginyeria de Sistemes, Automàtica i Informàtica Industrial, Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica, Universitat Politècnica de Catalunya. Centre de Desenvolupament Tecnològic de Sistemes d'Adquisició Remota i Tractament de la Informació (SARTI), Universitat Politècnica de Catalunya. SARTI - Centre de Desenvolupament Tecnològic de Sistemes d'Adquisició Remota i Tractament de la Informació |
| Jazyk: | angličtina |
| Rok vydání: | 2016 |
| Předmět: |
Contramesures electròniques
Coprocessor Correctness Computer Networks and Communications Computer science Side-channel analysis AES algorithm and hardware-software co-design 02 engineering and technology Encryption Artificial Intelligence Informàtica [Àrees temàtiques de la UPC] Countermeasure 0202 electrical engineering electronic engineering information engineering Side channel attack Hardware_ARITHMETICANDLOGICSTRUCTURES Field-programmable gate array Microprocessors Hardware architecture Virtex business.industry Electronic countermeasures Enginyeria electrònica [Àrees temàtiques de la UPC] Criptografia 020202 computer hardware & architecture Hardware and Architecture Embedded system Encriptació de dades (Informàtica) Key (cryptography) Cryptography Microprocessadors 020201 artificial intelligence & image processing business Software |
| Zdroj: | UPCommons. Portal del coneixement obert de la UPC Universitat Politècnica de Catalunya (UPC) Recercat. Dipósit de la Recerca de Catalunya instname |
| DOI: | 10.1016/j.micpro.2016.06.009 |
| Popis: | This paper aims at presenting a new countermeasure against Side-Channel Analysis (SCA) attacks, whose implementation is based on a hardware-software co-design. The hardware architecture consists of a microprocessor, which executes the algorithm using a false key, and a coprocessor that performs several operations that are necessary to retrieve the original text that was encrypted with the real key. The coprocessor hardly affects the power consumption of the device, so that any classical attack based on such power consumption would reveal a false key. Additionally, as the operations carried out by the coprocessor are performed in parallel with the microprocessor, the execution time devoted for encrypting a specific text is not affected by the proposed countermeasure. In order to verify the correctness of our proposal, the system was implemented on a Virtex 5 FPGA. Different SCA attacks were performed on several functions of AES algorithm. Experimental results show in all cases that the system is effectively protected by revealing a false encryption key. |
| Databáze: | OpenAIRE |
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