Application of Deep Compression Technique in Spiking Neural Network Chip
| Autor: | J. J. Wang, Rui Guo, Zhan Xitong, Yang Liu, Yong Liu, Yuancong Wu, Qian Kun, An Kun, S. G. Hu, Qi Yu, Tupei Chen, Sheng Xu |
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| Rok vydání: | 2019 |
| Předmět: |
Spiking neural network
Artificial neural network Computer science business.industry 020208 electrical & electronic engineering Models Neurological Biomedical Engineering 02 engineering and technology Equipment Design Chip Data Compression Network on a chip Scalability Synapses 0202 electrical engineering electronic engineering information engineering Neural Networks Computer Electrical and Electronic Engineering business Throughput (business) Energy (signal processing) MNIST database Computer hardware |
| Zdroj: | IEEE transactions on biomedical circuits and systems. 14(2) |
| ISSN: | 1940-9990 |
| Popis: | In this paper, a reconfigurable and scalable spiking neural network processor, containing 192 neurons and 6144 synapses, is developed. By using deep compression technique in spiking neural network chip, the amount of physical synapses can be reduced to 1/16 of that needed in the original network, while the accuracy is maintained. This compression technique can greatly reduce the number of SRAMs inside the chip as well as the power consumption of the chip. This design achieves throughput per unit area of 1.1 GSOP/( $\text{s}\!\cdot\!\text{mm}^2$ ) at 1.2 V, and energy consumed per SOP of 35 pJ. A 2-layer fully-connected spiking neural network is mapped to the chip, and thus the chip is able to realize handwritten digit recognition on MNIST with an accuracy of 91.2%. |
| Databáze: | OpenAIRE |
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