Automatic synthesis of an 8-bit CPU with 100% on-line error detection capability
| Autor: | J. Medero, N. Kanopoulos, T. Markas, E. Edwards, S. Wang |
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| Předmět: |
business.industry
Computer science Circuit design Mixed-signal integrated circuit Circuit extraction Computer engineering Application-specific integrated circuit Hardware_INTEGRATEDCIRCUITS Benchmark (computing) Physical design business Computer hardware Hardware_LOGICDESIGN Asynchronous circuit Register-transfer level |
| Zdroj: | Nick Kanopoulos ICECS |
| Popis: | This paper presents the use of a CAD system that allows the automatic synthesis of integrated circuits with on-line, 100% error detection capability. An 8-bit CPU serves as a benchmark to demonstrate the circuit technology used to automatically synthesize this type of circuit. The paper presents results on the actual design of the benchmark circuit and the use of the CAD system that made the design possible. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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