A 55nm Ultra Low Leakage Deeply Depleted Channel technology optimized for energy minimization in subthreshold SRAM and logic
| Autor: | Akihiko Harada, Taiji Ema, Harsh N. Patel, Makoto Yasuda, Farah B. Yahya, Benton H. Calhoun, Ningxi Liu, Kazuyuki Kumeno, Abhishek Roy |
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| Rok vydání: | 2016 |
| Předmět: |
Engineering
Finite impulse response Subthreshold conduction business.industry 020208 electrical & electronic engineering Electrical engineering Biasing Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Chip 020202 computer hardware & architecture Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering Static random-access memory business AND gate Random dopant fluctuation Leakage (electronics) |
| Zdroj: | ESSCIRC |
| DOI: | 10.1109/essderc.2016.7599583 |
| Popis: | This paper presents an Ultra-Low Leakage (ULL) 55nm Deeply Depleted Channel (DDC) process technology for low power Internet of Things (IoT) applications. The DDC ULL devices provide 67% reduction in threshold (V T ) variation due to Random Dopant Fluctuation (RDF). Circuit techniques such as subthreshold operation and reverse body biasing (RBB) are co-designed with the technology to maximize the energy/power saving. A test chip implements a 1Kb 6T SRAM, an FIR filter, and a 51-stage RO to showcase how the technology works with circuit techniques to minimize energy. The 6T SRAM array operates reliably down to 200mV with a reduced leakage power of 7nW (85% lower compared to non-DDC devices). The FIR filter consumes just 4.5pJ/cycle operating at 0.36V at 200 KHz. |
| Databáze: | OpenAIRE |
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