(Invited) Gate-All-Around Transistors Based on Vertically Stacked Si Nanowires
| Autor: | Geert Mannaert, Lars-Ake Ragnarsson, Els Van Besien, A. Dangol, Adrian Chasin, Diana Tsvetanova, Soon Aik Chew, S. Kubicek, Romain Ritzenthaler, Harold Dekkers, Andriy Hikavyy, Dan Mocuta, Hans Mertens, Naoto Horiguchi, Yoshiaki Kikuchi, Tom Schram, Erik Rosseel, An De Keersgieter, Zheng Tao, Kathy Barla, Katia Devriendt, Eddy Kunnen, Toby Hopf, Min-Soo Kim, Kurt Wostyn, Steven Demuynck |
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| Rok vydání: | 2017 |
| Předmět: | |
| Zdroj: | ECS Transactions. 77:19-30 |
| ISSN: | 1938-5862 1938-6737 |
| Popis: | Gate-all-around (GAA) transistors based on vertically stacked horizontal nanowires are promising candidates to replace FinFETs in future CMOS technology nodes. First of all, GAA devices provide optimal electrostatic control over semiconducting nanowire channels, which enables downscaling of the gate length to below the FinFET limit, while maintaining low off-state leakage [1]. Besides, horizontally oriented nanowires are an evolutionary extension of FinFETs, as opposed to vertical nanowires which require more disruptive technology and design changes [2]. Finally, stacking of nanowires is relevant for enhancing the drive current per footprint. Based on these considerations, GAA transistors made of vertically stacked horizontal nanowires have been included in the ITRS roadmap to reduce the contacted gate pitch, which is a key figure of merit for CMOS device density, to below ~40 nm in 2019-2021 [3]. In the context of the industrial relevance described above, we present the fabrication of Si GAA devices on bulk Si substrates. Multiple processing aspects that are relevant for bulk CMOS technology definition are addressed, including stacking of 8-nm-diameter Si wires at 45-nm lateral pitch and 20-nm vertical pitch [4], and nanowire-compatible replacement metal gate processing in combination with threshold voltage tuning by dual work function metal integration [5]. Temperature restrictions for the formation of shallow trench isolation, and the interaction between N- and P-type junction formation on one hand and nanowire release processes on the other hand are discussed as well. [1] K. J. Kuhn, IEEE Trans. Electron Devices, vol. 59 (7), p.1813, (2012). [2] L. Liebmann et al., VLSI Tech. Dig., p.112 (2016). [3] The International Roadmap for Semiconductors (ITRS) 2.0, http://www.itrs2.net/ (2015). [4] H. Mertens et al., VLSI Tech. Dig., p.158 (2016). [5] H. Mertens et al., IEDM Tech. Dig., p.524 (2016). Figure 1 |
| Databáze: | OpenAIRE |
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