Implementation of a burst error and burst erasure channel emulator using an FPGA architecture
| Autor: | Francesca Vatta, Fulvio Babich, Caterina Travan, Massimo Rigo |
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| Přispěvatelé: | IEEE, Rigo, Massimo, Travan, Caterina, Vatta, Francesca, Babich, Fulvio |
| Rok vydání: | 2014 |
| Předmět: |
Computer science
Real-time computing l burst error channel Data_CODINGANDINFORMATIONTHEORY Communications system Binary erasure channel Burst error Hardware emulation FPGA burst erasure chann l burst error channel hardware emulation burst erasure chann Forward error correction Field-programmable gate array hardware emulation FPGA Communication channel Data transmission |
| Zdroj: | SoftCOM |
| Popis: | In this paper, the hardware implementation of a burst error channel and a burst erasure channel simulator in Cyclone II Field Programmable Gate Array (FPGA) is proposed. In telecommunications, a burst error channel is a data transmission channel in which errors occur in a contiguous sequence of symbols, such that the first and last symbols are in error and there exists no contiguous subsequence of m correctly received symbols within the error burst. An erasure channel is one in which each transmitted symbol is either received correctly or is corrupted so badly as to be considered erased. When the erasures are clustered together we refer to the channel as a burst erasure channel. Although software simulations are easy to set up to simulate a transmission channel behavior, they are very time consuming. In order to speed up the communication system performance evaluation process and the final parameter optimization design, direct hardware emulation is proposed and presented. The implementation can be easily extended to other FPGA architectures. |
| Databáze: | OpenAIRE |
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