Revisited RF Compact Model of Gate Resistance Suitable for High- $K$/Metal Gate Technology

Autor: Francois Danneville, Patrick Scheer, B. Dormieu, C. Charbuillet, H. Jaouen
Přispěvatelé: Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520 (IEMN), Centrale Lille-Institut supérieur de l'électronique et du numérique (ISEN)-Université de Valenciennes et du Hainaut-Cambrésis (UVHC)-Université de Lille-Centre National de la Recherche Scientifique (CNRS)-Université Polytechnique Hauts-de-France (UPHF)
Rok vydání: 2013
Předmět:
Zdroj: IEEE Transactions on Electron Devices
IEEE Transactions on Electron Devices, Institute of Electrical and Electronics Engineers, 2013, 60, pp.13-19. ⟨10.1109/TED.2012.2225146⟩
IEEE Transactions on Electron Devices, 2013, 60, pp.13-19. ⟨10.1109/TED.2012.2225146⟩
ISSN: 1557-9646
0018-9383
DOI: 10.1109/ted.2012.2225146
Popis: State-of-the-art compact models of gate access resistance are investigated and compared with RF measurements for 28-nm high-k/metal gate MOS transistors. This work shows that the usual lumped gate resistance model fails to capture both geometry scaling and voltage dependence observed on silicon. The increasing role of the interface resistance is highlighted, and an improved gate access resistance model is proposed, featuring an encapsulation of the interface resistance component by parasitic capacitances. Theoretical insights and relevance of this new distributed model and associated parameters are also discussed.
Databáze: OpenAIRE