Performance Characterization and Majority Gate Design for MESO-Based Circuits
| Autor: | Sachin S. Sapatnekar, Jiaxi Hu, Zhaoxin Liang, Zhengyang Zhao, Meghna G. Mankalale, Jian-Ping Wang |
|---|---|
| Jazyk: | angličtina |
| Rok vydání: | 2018 |
| Předmět: |
lcsh:Computer engineering. Computer hardware
Computer science Generalization Computation lcsh:TK7885-7895 02 engineering and technology 01 natural sciences 0103 physical sciences Electronic engineering Logic error Electrical and Electronic Engineering 010306 general physics Electronic circuit Structure (mathematical logic) spintronics Inverse spin-orbit coupling (ISOC) 021001 nanoscience & nanotechnology simulation Electronic Optical and Magnetic Materials Power (physics) Hardware and Architecture Logic gate Inverter magnetoelectric (ME) coupling majority gate 0210 nano-technology |
| Zdroj: | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, Vol 4, Iss 2, Pp 51-59 (2018) |
| ISSN: | 2329-9231 |
| Popis: | Magnetoelectric spin-orbit (MESO) logic is a promising spin-based post-CMOS logic computation paradigm. This paper explores the application of the basic MESO device concept to more complex logic structures. A simulation framework is first developed to facilitate the performance evaluation of MESO-based circuits. Based on the analysis, it is seen that inadvertent logic errors may potentially be introduced in cascaded MESO stages due to sneak paths, and solutions for overcoming this problem with a short pulse and two-phase evaluation are discussed. Next, the generalization of the MESO inverter structure to majority logic gates is shown. Two implementations, based on different physical mechanisms, are presented and a relative analysis of their speed and power characteristics is provided. |
| Databáze: | OpenAIRE |
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