A 1.25 MHz, 108 dB Chopped Sampling-Mixer-Based Impedance Spectroscopy SoC in 0.18-μm CMOS
| Autor: | Hyeonsik Kim, Heejune Lee, Jintae Kim |
|---|---|
| Jazyk: | angličtina |
| Rok vydání: | 2022 |
| Předmět: |
Computer Networks and Communications
Hardware and Architecture Control and Systems Engineering Signal Processing Electrical and Electronic Engineering electrochemical impedance spectroscopy (EIS) direct digital frequency synthesizer (DDFS) impedance analyzer pipelined successive approximation register (SAR) analog-to-digital converter (ADC) |
| Zdroj: | Electronics; Volume 11; Issue 24; Pages: 4130 |
| ISSN: | 2079-9292 |
| DOI: | 10.3390/electronics11244130 |
| Popis: | This paper presents an electrochemical impedance spectroscopy (EIS) system-on-chip in 0.18-μm CMOS, achieving a wide scan frequency range of 1.25 MHz. An on-chip direct digital frequency synthesizer generates a digital sine wave as well as in-phase and quadrature-phase clocks that are synchronized to the sinewave. A chopped sampling mixer realizes lock-in detection without requiring quadrature sinewaves while suppressing low-frequency noise and offset. The receive utilizes a 12-bit pipelined SAR ADC operating in 5 MS/s in combination with a digital averaging filter to maximize the dynamic range. The measured performance shows that the prototype EIS chip achieves the highest frequency scan range with a comparable dynamic range of 108 dB and power consumption of 14 mW when compared with the previous state-of-the-art prototypes. |
| Databáze: | OpenAIRE |
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