Design of a pseudo-log image transform IP in an HLS-based memory management framework
| Autor: | Luciano Lavagno, Stéphane Mancini, Frédéric Rousseau, Shahzad Ahmad Butt |
|---|---|
| Přispěvatelé: | Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS), Dipartimento di Automatica e Informatica [Torino] (DAUIN), Politecnico di Torino = Polytechnic of Turin (Polito), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Politecnico di Torino [Torino] (Polito) |
| Rok vydání: | 2013 |
| Předmět: |
Flat memory model
Memory hierarchy business.industry Computer science Design space exploration Uniform memory access IP-designs Overlay Memory map Extended memory Memory address Memory management PACS 85.42 Computer data storage Virtual memory Computing with Memory Memory segmentation [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics business design-tools Computer hardware Auxiliary memory |
| Zdroj: | Real-Time Image and Video Processing Proceedings of Conference of Real-Time Image and Video Processing Conference of Real-Time Image and Video Processing Conference of Real-Time Image and Video Processing, Feb 2013, Burlingame, California, United States. 15 p., ⟨10.1117/12.2004272⟩ |
| ISSN: | 0277-786X |
| Popis: | ISBN : 978-08-19-494-290; International audience; The pseudo-log image transform is essentially a logarithmic transformation that simulates the distribution of the eye's photoreceptors and finds application in many important areas of real time image and video processing such as motion detection and estimation in robots and foveated space variant cameras. It belongs to a family of non-linear image processing kernels in which references made to memory are non-linear functions of loop indices. Non-linear kernels need some form of memory management in order to achieve the required throughput, to minimize on-chip memory and to maximize possible data re-use. In this paper we present the design of a pseudo-log image processing hardware accelerator IP, integrated with different interpolation filtering techniques, using a memory management framework. The framework can automatically generate a memory hierarchy around the IP and a data transfer controller that facilitates data exchange with main memory. The memory hierarchy reduces on-chip memory requirements, optimizes throughput and increases data-reuse. The design of the IP is fully performed at the algorithmic level in C/C++. The algorithmic description is profiled within the framework to create a customized memory hierarchy, also described at the synthesizable algorithmic level. Finally, high level synthesis is used to perform hardware design space exploration and performance estimation. Experiments show that the generated memory hierarchy is able to feed the IP with a very high bandwidth even in presence of long external memory latencies. |
| Databáze: | OpenAIRE |
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