First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers
| Autor: | Liesbeth Witters, Z. Wu, Anne Vandooren, G. Mannaert, Nadine Collaert, E. Vecchio, Lars-Ake Ragnarsson, Romain Ritzenthaler, Niamh Waldron, V. De Heyn, Jerome Mitard, Nouredine Rassoul, Boon Teik Chan, Dan Mocuta, Bertrand Parvais, Veeresh Deshpande, Fumihiro Inoue, Lan Peng, Andriy Hikavyy, G. Jamieson, J. Franco, W. Vanherle, Lieve Teugels, T. Zheng, W. Li, Amey Mahadev Walke, Katia Devriendt, Erik Rosseel, Julien Ryckaert, Nancy Heylen, Steven Demuynck, Geert Hellings, Juergen Boemmels |
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| Přispěvatelé: | Faculty of Economic and Social Sciences and Solvay Business School, Electronics and Informatics, Faculty of Engineering, Faculty of Medicine and Pharmacy, Human Physiology and Special Physiology of Physical Education, Vriendenkring VUB |
| Rok vydání: | 2018 |
| Předmět: |
010302 applied physics
Materials science Silicon business.industry Stacking chemistry.chemical_element 02 engineering and technology Dielectric Condensed Matter Physics 021001 nanoscience & nanotechnology 01 natural sciences Electronic Optical and Magnetic Materials Threshold voltage Dipole chemistry 0103 physical sciences Materials Chemistry Optoelectronics Wafer Electrical and Electronic Engineering 0210 nano-technology Tin business Immersion lithography |
| Zdroj: | 2018 IEEE International Electron Devices Meeting (IEDM). |
| DOI: | 10.1109/iedm.2018.8614654 |
| Popis: | 3 Dstacking using a sequential integration approach is demonstrated for finfet devices on 300mm wafers at a 45nm fin pitch and 110nm poly pitch technology. This demonstrates the compatibility of the 3D sequential approach for aggressive device density stacking at advanced nodes thanks to the tight alignment precision of the first processed top layer to the last processed bottom layer through the top silicon channel and bonding stack during 193nm immersion lithography. The top devices are junction-less devices fabricated at low temperature $(\mathrm{T}\leq 525^{\circ}\mathrm{C})$ in a top Si layer transferred by wafer-to-wafer bonding with a bonding dielectric stack down to 170nm. The top devices offer similar performance as the high temperature bulk finfet technology for LSTP applications. The use of TiN/TiA1/TiN/HfO 2 gate stack provides the proper threshold voltage adjustment while the insertion of the LaSiO x dipole improves device performance and brings the BTI reliability within specification at low temperature. |
| Databáze: | OpenAIRE |
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