Optimizing Pseudo-Random Built-In Self-Testing of Fully Synchronous as well as Multisynchronous Networks-on-Chip
| Autor: | Alessandro Strano, Davide Bertozzi, Nicola Caselli, Simone Terenzi |
|---|---|
| Jazyk: | angličtina |
| Rok vydání: | 2013 |
| Předmět: |
Pseudorandom number generator
Interconnection Engineering business.industry 020206 networking & telecommunications 02 engineering and technology Automatic test pattern generation Chip 020202 computer hardware & architecture Microarchitecture Network on a chip Built-in self-test Computer engineering Hardware and Architecture Embedded system Fault coverage 0202 electrical engineering electronic engineering information engineering Electrical and Electronic Engineering business Software |
| Zdroj: | IET Computers & Digital Techniques |
| Popis: | Most built-in self-test architectures use pseudo-random test pattern generators. However, whenever this technique has been applied to on-chip interconnection networks, overly large testing latencies have been reported. On the other hand, alternative approaches either suffer from large area penalties (like scan-based testing or the use of deterministic test patterns) or poor fault coverage in the control path (functional testing). Moreover, the recent proliferation of clock domains on a chip makes testing overly challenging. This manuscript presents the optimisation of a built-in self-testing framework based on pseudo-random test patterns to the microarchitecture of network-on-chip switches. As a result, fault coverage and testing latency approach those achievable with deterministic test patterns while materialising relevant area savings and enhanced flexibility. Finally, the authors implement the extension of the proposed testing methodology to multisynchronous systems, thus making it compliant with the relaxation of synchronisation assumptions in nanoscale designs. |
| Databáze: | OpenAIRE |
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