A 14 nm SoC platform technology featuring 2nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for low power, high performance and high density SoC products

Autor:	J. Lee, P. Bai, T. Leo, S. K.-Y. Shi, P. Vandervoorn, D. Ingerly, L. Rockford, Ramaswamy Rahul, Y.-W. Chen, Nidhi Nidhi, F. Al-Amoody, M. Jang, K. Byon, T. Rana, Curtis Tsai, A. Zainuddin, C. Quincy, Eric Karl, L. Yang, Hafez Walid M, Chetan Prasad, C. Petersburg, Olac-Vaw Roman W, K. Komeyli, A. Kumar, Chang Hsu-Yu, Anand Subramaniam, N. L. Dias, Tsung-Yuan Chang, H. Kilambi, K. Phoa, Pei-Chi Liu, Chen-Guan Lee, C.-H. Jan
Rok vydání:	2015
Předmět:	Materials science business.industry Transistor Electrical engineering High voltage law.invention PMOS logic law Logic gate Wide dynamic range Optoelectronics Static random-access memory business NMOS logic Leakage (electronics)
Zdroj:	VLSIC
Popis:	A leading edge 14 nm SoC platform technology based upon the 2nd generation Tri-Gate transistor technology [5] has been optimized for density, low power and wide dynamic range. 70 nm gate pitch, 52 nm metal pitch and 0.0499 um2 HDC SRAM cells are the most aggressive design rules reported for 14/16 nm node SoC process to achieve Moore's Law 2x density scaling over 22 nm node. High performance NMOS/PMOS drive currents of 1.3/1.2 mA/um, respectively, have been achieved at 0.7 V and 100 nA/um off-state leakage, 37%/50% improvement over 22 nm node. Ultra-low power NMOS/PMOS drives are 0.50/0.32 mA/um at 0.7 V and 15pA/um Ioff. This technology also deploys high voltage I/O transistors to support up to 3.3 V I/O. A full suite of analog, mixed-signal and RF features are also supported.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_dedup___::3ad023e07edda7779db811903bcb46fb https://doi.org/10.1109/vlsic.2015.7231380 Zobrazit plný text záznamu