WDDL is Protected Against Setup Time Violation Attacks
| Autor: | Sylvain Guilley, Nidhal Selmane, Shivam Bhasin, Jean-Luc Danger, Tarik Graba |
|---|---|
| Přispěvatelé: | Laboratoire Traitement et Communication de l'Information (LTCI), Télécom ParisTech-Institut Mines-Télécom [Paris] (IMT)-Centre National de la Recherche Scientifique (CNRS), SeFPGA, ANR-07-ARFU-0010,SEFPGA,Architectures FPGA hiérarchiques sécurisées pour les systèmes sur puce(2007) |
| Jazyk: | angličtina |
| Rok vydání: | 2009 |
| Předmět: |
Computer science
Cryptography 02 engineering and technology Fault (power engineering) Encryption Computer security computer.software_genre [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR] Ciphertext 0202 electrical engineering electronic engineering information engineering Protection against faults Side channel attack Hardware_ARITHMETICANDLOGICSTRUCTURES Field-programmable gate array FPGA AES business.industry WDDL 020206 networking & telecommunications 020202 computer hardware & architecture Setup violation fault attacks Null (SQL) Logic gate [INFO.INFO-ES]Computer Science [cs]/Embedded Systems business computer |
| Zdroj: | FDTC CHES CHES, Sep 2009, Lausanne, Switzerland. pp.73-83, ⟨10.1109/FDTC.2009.40⟩ |
| Popis: | 73-83; International audience; In order to protect crypto-systems against side channel attacks various countermeasures have been implemented such as dual-rail logic or masking. Faults attacks are a powerful tool to break some implementations of robust cryptographic algorithms such as AES and DES. Various kind of fault attacks scenarios have been published. However, very few publications available in the public literature detail the practical realization of such attacks. In this paper we present the result of a practical fault attack on AES in WDDL and its comparison with its non-protected equivalent. The practical faults on an FPGA running an AES encryptor are realized by under-powering it and further exploited using Piret's attack. The results show that WDDL is protected against setup violation attacks by construction because a faulty bit is replaced by a null bit in the ciphertext. Therefore, the fault leaks no exploitable information. We also give a theoretical model for the above results. Other references have already studied the potential of fault protection of the resynchronizing gates (delayinsensitive). In this paper, we show that non-resynchronizing gates (hence combinatorial DPL such as WDDL) are natively immune to setup time violation attacks. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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