SAFEPOWER project: Architecture for safe and power-efficient mixed-criticality systems
| Autor: | Razi Seyyedi, Roman Obermaisser, Javier Coronel, Alfons Crespo, J.C. García, Mohamed Tagelsir Mohammadat, Johnny Öberg, Sören Schreiner, Alina Lenz, Adele Maleki, Nera González Romero, Jon Perez, Mikel Azkarate-askasua, Ingo Sander, Kim Grüttner, Ingemar Söderquist, Simon Davidmann, Maher Fakih |
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| Rok vydání: | 2017 |
| Předmět: |
Mixed criticality
Computer Networks and Communications Computer science business.industry Reliability (computer networking) 020208 electrical & electronic engineering 02 engineering and technology Avionics 7. Clean energy 020202 computer hardware & architecture Power (physics) Criticality Artificial Intelligence Hardware and Architecture Embedded system 0202 electrical engineering electronic engineering information engineering System on a chip business Electrical efficiency Software Efficient energy use |
| Zdroj: | Microprocessors and Microsystems. 52:89-105 |
| ISSN: | 0141-9331 |
| Popis: | With the ever increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible without regarding their criticality. Even safety critical domains like railway and avionics apply these paradigms under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such System on Chip (SoC) is to enhance the way the SoC handles its power resources. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power saving methods in safety critical domains yet. The EU project SAFEPOWER1 targets this research gap and aims to introduce certifiable methods to improve the power efficiency of mixed-criticality real-time systems (MCRTES). This article will introduce the requirements that a power efficient SoC has to meet and the challenges such a SoC has to overcome. |
| Databáze: | OpenAIRE |
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