High throughput/gate AES hardware architectures based on datapath compression
| Autor: | Kohei Matsuda, Naofumi Homma, Noriyuki Miura, Shivam Bhasin, Rei Ueno, Tarik Graba, Makoto Nagata, Jean-Luc Danger, Sumio Morioka, Yves Mathieu |
|---|---|
| Přispěvatelé: | Nanyang Technopreneurship Center, Research Techno Plaza, Tohoku University [Sendai], Interstellar Technologies Inc., Hokkaido, Konan University [Kobe, Japan], Nanyang Technological University [Singapour], Secure and Safe Hardware (SSH), Laboratoire Traitement et Communication de l'Information (LTCI), Institut Mines-Télécom [Paris] (IMT)-Télécom Paris-Institut Mines-Télécom [Paris] (IMT)-Télécom Paris, Département Communications & Electronique (COMELEC), Télécom ParisTech, Institut Mines-Télécom [Paris] (IMT)-Télécom Paris, Télécom ParisTech-Institut Mines-Télécom [Paris] (IMT)-Télécom ParisTech-Institut Mines-Télécom [Paris] (IMT), Télécom ParisTech-Institut Mines-Télécom [Paris] (IMT) |
| Jazyk: | angličtina |
| Rok vydání: | 2019 |
| Předmět: |
Block cipher mode of operation
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR] Hardware Architectures Computer science Cryptography 02 engineering and technology Encryption Theoretical Computer Science [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR] Round-Based Encryption Architecture Datapath 0202 electrical engineering electronic engineering information engineering [INFO.INFO-DL]Computer Science [cs]/Digital Libraries [cs.DL] ComputingMilieux_MISCELLANEOUS business.industry [INFO.INFO-AO]Computer Science [cs]/Computer Arithmetic Advanced Encryption Standard [INFO.INFO-MO]Computer Science [cs]/Modeling and Simulation 020202 computer hardware & architecture [SPI.TRON]Engineering Sciences [physics]/Electronics Logic synthesis Computational Theory and Mathematics Hardware and Architecture Logic gate Electrical and electronic engineering [Engineering] business Software Computer hardware |
| Zdroj: | IEEE Transactions on Computers IEEE Transactions on Computers, Institute of Electrical and Electronics Engineers, 2020, 69 (4), pp.534-548. ⟨10.1109/TC.2019.2957355⟩ |
| ISSN: | 0018-9340 |
| Popis: | This article proposes highly efficient Advanced Encryption Standard (AES) hardware architectures that support encryption and both encryption and decryption. New operation-reordering and register-retiming techniques presented in this article allow us to unify the inversion circuits in SubBytes and InvSubBytes without any delay overhead. In addition, a new optimization technique for minimizing linear mappings, named multiplicative-offset, further enhances the hardware efficiency. We also present a shared key scheduling datapath that can work on-the-fly in the proposed architecture. To the best of our knowledge, the proposed architecture has the shortest critical path delay and is the most efficient in terms of throughput per area among conventional AES encryption/decryption and encryption architectures with tower-field S-boxes. The proposed round-based architecture can perform AES encryption where block-wise parallelism is unavailable (e.g., cipher block chaining (CBC) mode); thus, our techniques can be globally applied to any type of architecture including pipelined ones. We evaluated the performance of the proposed and some conventional datapaths by logic synthesis with the NanGate 45-nm open-cell library. As a result, we can confirm that our proposed architectures achieve approximately 51-64 percent higher efficiency (i.e., higher bps/GE) and lower power/energy consumption than the other conventional counterparts. Published version This research has been supported by JSPS KAKENHI Grant No. 17H00729 and No. 19K21526, and JST PRESTO Grant No. JPMJPR18M3. |
| Databáze: | OpenAIRE |
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