| Autor: |
Pei-Ing Lee, Jengping Lin, Minchen Chang, S.N. Shih, Ruey-Dar Chang, Chao-Sung Lai |
| Rok vydání: |
2004 |
| Předmět: |
|
| Zdroj: |
Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2004 (IEEE Cat. No.04TH8743). |
| Popis: |
The data retention time performance of 256 Mbit DRAM is degraded even in a 250/spl deg/C packaging process. The retention time degradation is strongly dependent on the negative wordline voltage and operation temperature. Trap-assisted gate induced drain leakage is proposed as the mechanism for the retention degradation based on electrical testing and simulation. It is believed that silicon-hydrogen bond breaking and moving at the gate and drain overlap region of an array transistor is the root cause of retention degradation. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
|
