Power Efficient UART Design Using Capacitive Load on Different Nanometer Technology FPGA
| Autor: | Keshav Kumar, D. M. Akbar Hussain, Bishwajeet Pandey |
|---|---|
| Jazyk: | angličtina |
| Rok vydání: | 2019 |
| Předmět: |
Universal asynchronous receiver/transmitter
business.industry Computer science Virtex-6 Virtex-5 Electrical engineering Virtex-4 Power efficient Capacitance Hardware_PERFORMANCEANDRELIABILITY Power factor Spartan-3 UART Spartan-6 Power analysis Hardware_GENERAL Hardware_INTEGRATEDCIRCUITS Nanometre Hardware_ARITHMETICANDLOGICSTRUCTURES business Field-programmable gate array Xilinx Hardware_LOGICDESIGN |
| Zdroj: | Kumar, K, Pandey, B & Hussain, D M A 2019, ' Power Efficient UART Design Using Capacitive Load on Different Nanometer Technology FPGA ', Gyancity Journal of Engineering and Technology, vol. 5, no. 2 . https://doi.org/10.21058/gjet.2019.52001 |
| DOI: | 10.21058/gjet.2019.52001 |
| Popis: | In this paper, we are changing the capacitance of the UART and observing the power at different value of capacitance. As we are changing the capacitance of UART not only power but the maximum temperature and junction temperature also get affected. As the value of capacitance increases and reaches 50000 pf or above in Virtex-4, Virtex-5, Virtex-6 the capacitor of the UART burns out and for Spartan-3 and Spartan-6 when capacitance value goes to 5000 pf or above the capacitor of the UART burns out. Burning of capacitor disturbs the communication of UART over longer distance. In this paper power analysis is done on Xilinx ISE Design 14.1 and the UART code is written in Verilog Hardware Description Language. Power analysis is done by changing the capacitance of the capacitor from 5 pf to 50,000 pf at different nanometer technology based FPGA that are Virtex-4, Virtex-5, Virtex-6, Spartan-3 and Spartan-6 respectively. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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