SystemC Transaction-Level Modeling of an MPSoC Platform Based on an Open Source ISS by Using Interprocess Communication
| Autor: | El-Bay Bourennane, S. Boukhechem |
|---|---|
| Jazyk: | angličtina |
| Rok vydání: | 2008 |
| Předmět: |
Open platform
lcsh:Computer engineering. Computer hardware Article Subject Modeling language Computer science business.industry lcsh:TK7885-7895 MPSoC Instruction set Computer architecture Hardware and Architecture SystemC Embedded system Transaction-level modeling Open architecture business computer Wishbone computer.programming_language |
| Zdroj: | International Journal of Reconfigurable Computing, Vol 2008 (2008) |
| ISSN: | 1687-7209 1687-7195 |
| Popis: | Transaction-level modeling (TLM) is a promising technique to deal with the increasing complexity of modern embedded systems. This model allows a system designer to model a complete application, composed of hardware and software parts, at several levels of abstraction. For this purpose, we use systemC, which is proposed as a standardized modeling language. This paper presents a transaction-level modeling cosimulation methodology for modeling, validating, and verifying our embedded open architecture platform. The proposed platform is an open source multiprocessor system-on-chip (MPSoC) platform, integrated under the synthesis tool for adaptive and reconfigurable system-on-chip (STARSoC) environment. It relies on the integration between an open source instruction set simulators (ISSs), OR1Ksim platform, and the systemC simulation environment which contains other components (wishbone bus, memories, , etc.). The aim of this work is to provide designers with the possibility of faster and efficient architecture exploration at a higher level of abstractions, starting from an algorithmic description to implementation details. |
| Databáze: | OpenAIRE |
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