A CMOS 0.18 μm 600 MHz clock multiplier PLL and a pseudo-LVDS driver for the high speed data transmission for the ALICE Inner Tracking System front-end chip
| Autor: | Andrei Dorokhov, M. Keil, G. L. Usai, Narong Chanlek, Luciano Musa, Antoine Jean-Simon Junique, J. Willem Van Hoorne, W. Snoeys, Dong Jo Kim, C. Puggioni, Felix Reidt, G. Mazza, Christophe Flouzat, C. Cavicchioli, F. Guilloux, Alberto Collu, Thanushan Kugathasan, Paolo Martinengo, C. Augusto Marin Tobon, D. Marras, Hartmut Hillemanns, Magnus Mager, M. Song, D. Gajanana, Ping Yang, K. Marek Sielewicz, Chaosong Gao, S. Siddhanta, T. Hung Pham, H. Mugnier, Alessandra Lattuca, S. Hristozkov, Monika Kofarago, Petra Riedler, G. Aglieri Rinella, J. Rousset, Y. J. Kwon, Yavuz Degerli |
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| Přispěvatelé: | Institut de Recherches sur les lois Fondamentales de l'Univers (IRFU), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université Paris-Saclay, Institut Pluridisciplinaire Hubert Curien (IPHC), Université de Strasbourg (UNISTRA)-Université de Haute-Alsace (UHA) Mulhouse - Colmar (Université de Haute-Alsace (UHA))-Institut National de Physique Nucléaire et de Physique des Particules du CNRS (IN2P3)-Centre National de la Recherche Scientifique (CNRS), Centre National de la Recherche Scientifique (CNRS) |
| Jazyk: | angličtina |
| Rok vydání: | 2015 |
| Předmět: |
Computer science
02 engineering and technology Integrated circuit design 010502 geochemistry & geophysics 01 natural sciences ALICE 0202 electrical engineering electronic engineering information engineering Hardware_INTEGRATEDCIRCUITS tracking detector [PHYS.PHYS.PHYS-INS-DET]Physics [physics]/Physics [physics]/Instrumentation and Detectors [physics.ins-det] Detectors and Experimental Techniques Hardware_ARITHMETICANDLOGICSTRUCTURES Double data rate signal processing Instrumentation Mathematical Physics 0105 earth and related environmental sciences business.industry 020208 electrical & electronic engineering Electrical engineering Chip Phase-locked loop CMOS integrated circuit: design electronics: readout Serializer business Data transmission CPU multiplier |
| Zdroj: | JINST Topical Workshop on Electronics for Particle Physics Topical Workshop on Electronics for Particle Physics, Sep 2015, Lisbon, Portugal. pp.C01066, ⟨10.1088/1748-0221/11/01/C01066⟩ |
| DOI: | 10.1088/1748-0221/11/01/C01066⟩ |
| Popis: | International audience; This work presents the 600 MHz clock multiplier PLL and the pseudo-LVDS driver which are two essential components of the Data Transmission Unit (DTU), a fast serial link for the 1.2 Gb/s data transmission of the ALICE inner detector front-end chip (ALPIDE). The PLL multiplies the 40 MHz input clock in order to obtain the 600 MHz and the 200 MHz clock for a fast serializer which works in Double Data Rate mode. The outputs of the serializer feed the pseudo-LVDS driver inputs which transmits the data from the pixel chip to the patch panel with a limited number of signal lines. The driver drives a 5.3 m-6.5 m long differential transmission line by steering a maximum of 5 mA of current at the target speed. To overcome bandwidth limitations coming from the long cables the pre-emphasis can be applied to the output. Currents for the main and pre-emphasis driver can individually be adjusted using on-chip digital-to-analog converters. The circuits will be integrated in the pixel chip and are designed in the same 0.18 μm CMOS technology and will operate from the same 1.8 V supply. Design and test results of both circuits are presented. |
| Databáze: | OpenAIRE |
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