Multi-granular arithmetic in a coarse-grain reconfigurable architecture
| Autor: | Mark Wijtvliet, Stef Louwers, Henk Corporaal, Ruud Koolen, Luc Waeijen |
|---|---|
| Přispěvatelé: | Electronic Systems |
| Jazyk: | angličtina |
| Rok vydání: | 2016 |
| Předmět: |
Multiplication algorithm
Computer science BLOCKS Energy Efficiency Context (language use) Parallel computing Operand CGRA Arbitrary-precision arithmetic Multi-Granular Arithmetic Saturation arithmetic Multiplication Multiplier (economics) SDG 7 - Affordable and Clean Energy Arithmetic Hardware_ARITHMETICANDLOGICSTRUCTURES SDG 7 – Betaalbare en schone energie Efficient energy use |
| Zdroj: | DSD Proceedings-19th Euromicro Conference on Digital System Design, DSD 2016, 599-606 STARTPAGE=599;ENDPAGE=606;TITLE=Proceedings-19th Euromicro Conference on Digital System Design, DSD 2016 |
| DOI: | 10.1109/dsd.2016.98 |
| Popis: | Mismatch between operand width and hardware operation width is a source of energy inefficiency. This work proposes multi-granular arithmetic, which can adapt the hardware operation width to the application, preventing energy being wasted. In particular multi-granular arithmetic in the context of coarse-grain reconfigurable architectures is considered for the operations of addition, accumulation, multiplication, and multiply-accumulation. Using a silicon synthesis-toolflow it is shown that the multi-granular designs can perform narrow width operations, e.g. an 8-by-8 multiplication, much more efficiently than standard full-width circuits. For multiplication the required energy is reduced by up to 15 times under realistic conditions when compared to a full-width 32x32 multiplier. |
| Databáze: | OpenAIRE |
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