Reconsidering High-Speed Design Criteria for Transmission-Gate-Based Master–Slave Flip-Flops

Autor:	Gaetano Palumbo, Elio Consoli, M. Pennisi
Rok vydání:	2012
Předmět:	Engineering Correctness business.industry Master/slave Logic synthesis Computer engineering Transmission gate Hardware and Architecture Logic gate Electronic engineering Logical effort Minification Electrical and Electronic Engineering business Software Hardware_LOGICDESIGN Efficient energy use
Zdroj:	IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 20:284-295
ISSN:	1557-9999 1063-8210
DOI:	10.1109/tvlsi.2010.2098426
Popis:	In this paper we show that, when dealing with transmission-gate-based master-slave (TGMS) flip-flops (FFs), a reconsideration of the classical approach for the delay minimization is worthwhile to improve the performance in high-speed designs. In particular, by splitting such FFs into two sections that are separately optimized and then reconciling the results, the emerging design always outperforms the one resulting from the employment of a classical Logical Effort procedure assuming such FFs as a whole continuous path. Simulations are performed on several well-known TGMS FFs, designed in a 65-nm technology, to validate the correctness of such a procedure and of the underlying assumptions. Significant improvements are found on delay and, remarkably, on energy and area occupation, thus showing that this approach allows to correctly deal with the actual path effort in such circuits and hence to more properly steer the design towards the achievement of energy efficiency in the high-speed region.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_dedup___::33c942eaaf3a97b5f8ce9d57691333b1 https://doi.org/10.1109/tvlsi.2010.2098426 Zobrazit plný text záznamu