A 30-GHz Digital Sub-Sampling Fractional-N PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS
| Autor: | Salvatore Levantino, Luca Bertulessi, Saleh Karman, Andrea L. Lacaita, Carlo Samori, Dmytro Cherniak, Alessandro Garghetti |
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| Jazyk: | angličtina |
| Rok vydání: | 2019 |
| Předmět: |
Physics
Frequency synthesizer 020208 electrical & electronic engineering CMOS 02 engineering and technology Sawtooth wave Topology Phase detector Phase-locked loop Frequency divider Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Figure of merit Electrical and Electronic Engineering Jitter |
| Popis: | This article describes the implementation of a 30-GHz frequency synthesizer. The target is to reduce the gap in terms of jitter-power product that exists between millimeter-wave and RF synthesizers, using a low-cost 65-nm LP CMOS technology. The circuit is a digitally intensive fractional- ${N}$ phase-locked loop, which combines a sub-sampling bang-bang phase detector, a low-power divider-by-six prescaler with a novel injection scheme, and a digital technique reducing the output range of the digital-to-time-converter. The synthesizer can operate between 30.4 and 34.2 GHz with a frequency resolution of 191 Hz and with an integrated rms jitter below 180 and 197.6 fs for the integer- ${N}$ and fractional- ${N}$ channels, respectively. The sub-sampling loop can synthesize fast sawtooth chirps around 33.4 GHz with peak-to-peak amplitudes up to 1.14 GHz. The fractional spurs, measured at the 5-GHz prescaler output, are below −54 dBc, even considering near-integer channels. The power dissipation of 35 mW from the 1.2-V supply leads to a −238.6 dB of jitter-power figure of merit for fractional- ${N}$ channels. |
| Databáze: | OpenAIRE |
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