Digital Circuit for Seamless Resampling ADC Output Streams
| Autor: | Mauro D'Arco, Ettore Napoli, Efstratios Zacharelos |
|---|---|
| Přispěvatelé: | D'Arco, Mauro, Napoli, Ettore, Zacharelos, Efstratios |
| Jazyk: | angličtina |
| Rok vydání: | 2020 |
| Předmět: |
Computer science
Clock rate 02 engineering and technology lcsh:Chemical technology Biochemistry Article digital circuit design Analytical Chemistry Sampling (signal processing) Application-specific integrated circuit resampling 0202 electrical engineering electronic engineering information engineering lcsh:TP1-1185 Electrical and Electronic Engineering Oscilloscope Field-programmable gate array Instrumentation Digital signal processing FPGA Digital electronics business.industry ASIC 020208 electrical & electronic engineering interpolating polynomial Digital circuit design Interpolating polynomial Polyphase filter Resampling 020206 networking & telecommunications Atomic and Molecular Physics and Optics polyphase filter Memory management Digital storage oscilloscope business Digital filter Computer hardware |
| Zdroj: | Sensors (Basel, Switzerland) Sensors, Vol 20, Iss 6, p 1619 (2020) Sensors Volume 20 Issue 6 |
| Popis: | Fine resolution selection of the sample rate is not available in digital storage oscilloscopes (DSOs), so the user has to rely on offline processing to cope with such need. The paper first discusses digital signal processing based methods that allow changing the sampling rate by means of digital resampling approaches. Then, it proposes a digital circuit that, if included in the acquisition channel of a digital storage oscilloscope, between the internal analog-to-digital converter (ADC) and the acquisition memory, allows the user to select any sampling rate lower than the maximum one with fine resolution. The circuit relies both on the use of a short digital filter with dynamically generated coefficients and on a suitable memory management strategy. The output samples produced by the digital circuit are characterized by a sampling rate that can be incoherent with the clock frequency regulating the memory access. Both a field programmable gate array (FPGA) implementation and an application specific integrated circuit (ASIC) design of the proposed circuit are evaluated. |
| Databáze: | OpenAIRE |
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