A self-checking PLA automatic generator tool based on unordered codes encoding
| Autor: | Torki, K., Nicolaidis, M., Fernandes, A.-O. |
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| Přispěvatelé: | Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), iROc Technologies (IROC TECHNOLOGIES), Cadence Connection-EDA Consortium-FSA-Cubic Micro, Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS) |
| Rok vydání: | 2002 |
| Předmět: |
PLA-automatic-generator-tool
self-checking-circuits area-overhead concurrent-error-detection PACS 85.42 Hardware_INTEGRATEDCIRCUITS hardware-redundancy programmable-logic-arrays [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics Hardware_LOGICDESIGN unordered-codes-encoding |
| Zdroj: | EDAC.-Proceedings-of-the-European-Conference-on-Design-Automation. 1991 EDAC.-Proceedings-of-the-European-Conference-on-Design-Automation. 1991:, 1991, Amsterdam, Netherlands. pp.510-15, ⟨10.1109/EDAC.1991.206459⟩ |
| Popis: | Self-checking circuits ensure concurrent error detection by means of hardware redundancy. An important drawback of self-checking circuits is the fact that they involve a significant increasing of the design time. Specific CAD tools are needed in order to cope with this drawback. In this paper the authors present a tool allowing automatic generation of self-checking PLAs. Then they validate this tool by transforming a set of PLA benchmarks into self-checking PLAs and give statistics concerning the required area overhead. |
| Databáze: | OpenAIRE |
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