Novel Low-Complexity and Low-Power Flip-Flop Design
| Autor: | Jin-Fa Lin, Hong Zheng-Jie, Bo-Cheng Wu, Chang-Ming Tsai, Shao-Wei Yu |
|---|---|
| Jazyk: | angličtina |
| Rok vydání: | 2020 |
| Předmět: |
Pass transistor logic
Computer Networks and Communications Computer science Internet of Things lcsh:TK7800-8360 02 engineering and technology Hardware_PERFORMANCEANDRELIABILITY law.invention pass transistor logic law 0202 electrical engineering electronic engineering information engineering Electronic engineering Hardware_INTEGRATEDCIRCUITS Hybrid logic Electrical and Electronic Engineering Circuit complexity Flip-flop Shift register Digital electronics low power business.industry lcsh:Electronics 020208 electrical & electronic engineering 020202 computer hardware & architecture Semiconductor CMOS Transmission gate flip-flop Hardware and Architecture Control and Systems Engineering Signal Processing business Hardware_LOGICDESIGN |
| Zdroj: | Electronics Volume 9 Issue 5 Electronics, Vol 9, Iss 783, p 783 (2020) |
| ISSN: | 2079-9292 |
| DOI: | 10.3390/electronics9050783 |
| Popis: | In this paper, a compact and low-power true single-phase flip-flop (FF) design with fully static operations is presented. The design is developed by using various circuit-reduction schemes and features a hybrid logic style employing both pass transistor logic (PTL) and static complementary metal-oxide semiconductor (CMOS) logic to reduce circuit complexity. These circuit optimization measures pay off in various aspects, including smaller clock-to-Q (CQ) delay, lower average power, lower leakage power, and smaller layout area and the transistor-count is only 17. Fabricated in TSMC 180 nm CMOS technology, it reduces by over 29% the chip area compared to the conventional transmission gate FF (TGFF). To further show digital circuit/system level advantages, a multi-mode shift register has been realized. Experimental measurement results at 1.8 V/4 MHz show that, compared with the TGFF design, the proposed design saves 64.7% of power consumption while reducing chip area by 26.2%. |
| Databáze: | OpenAIRE |
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