| Popis: |
Digital control for low-cost high-frequency dc-dc converters requires a reduced number of bit for Analog to Digital Converters (ADCs). By assuming that the sampled variable exhibits a linear behavior during switch-on and switch-off phases, this paper investigates a simple method to increase the ADC resolution using a low resolution Digital to Analog Converter (DAC) and a comparator. The digital estimation is performed using geometrical considerations and assuming the knowledge of the slope of the triangular ripple waveform. The estimation algorithm requires only a rough knowledge of system parameters and it can be easily self-adjusted. Applications to current loop control, VRM control, output voltage control with electrolytic output capacitors are reported. Simulation and experimental results of a synchronous buck converter (1.3V–10 A) using a Field Programmable Gate Array (FPGA) confirm the properties of the proposed investigation. |
