An Approach to Decrease Dimentions of Logical Elements Based On Bipolar Transistor
Autor: | E.L.Pankratov, E.A.Bulaeva |
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Rok vydání: | 2015 |
Předmět: |
Transistor-transistor logic
Condensed Matter::Materials Science analytical approach for modelling Hardware_INTEGRATEDCIRCUITS Hardware_PERFORMANCEANDRELIABILITY Condensed Matter::Mesoscopic Systems and Quantum Hall Effect optimization of manufacturing decreasing of dimensions of transistor Hardware_LOGICDESIGN |
Zdroj: | International Journal on Computational Science & Applications. 5:01-18 |
ISSN: | 2200-0011 |
DOI: | 10.5121/ijcsa.2015.5401 |
Popis: | In this paper we consider manufacturing logical elements with function AND-NOT based on bipolar transistors. Based on recently considered approach to decrease dimensions of solid state electronic devices with the same time increasing of their performance we introduce an approach to decrease dimensions of transistors and p-n-junctions, which became a part of the logical element. Framework the approach a heterostructure with required configuration should be manufactured. After the manufacture required areas of the heterostructures should be doped by diffusion or ion implantation. The doping should be finished by optimized annealing of dopant and/or radiation defects |
Databáze: | OpenAIRE |
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