SRAM Arrays with Built-in Parity Computation for Real-Time Error Detection in Cache Tag Arrays
| Autor: | Arkady Bramnik, Yiannakis Sazeides, Ramon Canal |
|---|---|
| Přispěvatelé: | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya. VIRTUOS - Virtualisation and Operating Systems |
| Rok vydání: | 2021 |
| Předmět: |
Error-correcting codes (Information theory)
Codis de correcció d'errors (Teoria de la informació) Error detection and correction Computer science business.industry Computation Serialization SRAM array Real-time data processing Tag array Reliability Fault (power engineering) Real-time error detection (RTD) Cache Static random-access memory business Informàtica::Arquitectura de computadors [Àrees temàtiques de la UPC] Temps real (Informàtica) Energy (signal processing) Access time Computer hardware |
| Zdroj: | DATE UPCommons. Portal del coneixement obert de la UPC Universitat Politècnica de Catalunya (UPC) |
| DOI: | 10.23919/date51398.2021.9473986 |
| Popis: | This work proposes an SRAM array with built-in real-time error detection (RTD) capabilities. Each cell in the new RTD-SRAM array computes its part of the real-time parity of an SRAM array column on-the-fly. RTD based arrays detect a fault right away after it occurs, rather than when it is read. RTD, therefore, breaks the serialization between data access and error detection and, thus, it can speed-up the access-time of arrays that use on-the-fly error detection and correction. The paper presents an analysis and optimization of an RTD-SRAM and its application to a tag array. Compared to a state-of-the-art tag array protection, the evaluated scheme has comparable error detection and correction strength and, depending on the array dimensions, the access time is reduced by 5% to 18%, energy by 20% to 40% and area up to 30%. |
| Databáze: | OpenAIRE |
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