Track finding mezzanine for Level-1 triggering in HL-LHC experiments
| Autor: | Guillaume Baulieu, C. Gentsos, Francesco Crescioli, Giacomo Fedi, Atanu Modak, Loriano Storchi, G. Galbit, Denis Tcherniakhovski, Suvankar Roy Chowdhury, L. Servoli, Spiridon Nikolaidis, Matthias Balzer, D. Magalotti, Nicolo Vladi Biesuz, Sébastien Viret, Fabrizio Palla, Guido Magazzu, Gian Mario Bilei, Oliver Sander, B. Checcucci |
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| Přispěvatelé: | Laboratoire de Physique Nucléaire et de Hautes Énergies (LPNHE (UMR_7585)), Institut National de Physique Nucléaire et de Physique des Particules du CNRS (IN2P3)-Université Paris Diderot - Paris 7 (UPD7)-Sorbonne Université (SU)-Centre National de la Recherche Scientifique (CNRS), Institut de Physique Nucléaire de Lyon (IPNL), Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Université de Lyon-Institut National de Physique Nucléaire et de Physique des Particules du CNRS (IN2P3)-Centre National de la Recherche Scientifique (CNRS), Institut National de Physique Nucléaire et de Physique des Particules du CNRS (IN2P3)-Sorbonne Université (SU)-Centre National de la Recherche Scientifique (CNRS)-Université de Paris (UP), Centre National de la Recherche Scientifique (CNRS)-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Université de Lyon-Institut National de Physique Nucléaire et de Physique des Particules du CNRS (IN2P3) |
| Rok vydání: | 2017 |
| Předmět: |
application specific integrated circuits
Engineering PRM FPGAs FPGA devices pattern recognition mezzanine Poles and towers Application-specific integrated circuit HL-LHC experiments associative memory ASICs Pattern recognition Content-addressable storage [PHYS.PHYS.PHYS-INS-DET]Physics [physics]/Physics [physics]/Instrumentation and Detectors [physics.ins-det] Pattern matching Latency (engineering) latency constraints Field-programmable gate array Real-time systems Real-time operating system FPGA track finding mezzanine Large Hadron Collider track data analysis business.industry trigger circuits Associative memory level-1 triggering integrated circuit content-addressable storage Real time systems Field programmable gate arrays trigger high luminosity upgrade CERN large hadron collider Content-addressable memory Roads CERN LHC Coll Embedded system real-time system business electronics: design tracker information extraction |
| Zdroj: | MOCAST 6th International Conference on Modern Circuits and Systems Technologies 6th International Conference on Modern Circuits and Systems Technologies, May 2017, Thessaloniki, Greece. pp.7937676, ⟨10.1109/MOCAST.2017.7937676⟩ |
| DOI: | 10.1109/mocast.2017.7937676 |
| Popis: | International audience; The increase of the luminosity in the High Luminosity upgrade of the CERN Large Hadron Collider (HL-LHC) will require the use of Tracker information in the evaluation of the Level-1 trigger in order to keep the trigger rate acceptable (i.e. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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