A NOVEL MIFGMOS TRANSISTOR BASED APPROACH FOR THE REALIZATION OF TERNARY GATES
| Autor: | Satish S. Narkhede, Bharat S. Chaudhari, G K Kharate |
|---|---|
| Jazyk: | angličtina |
| Rok vydání: | 2015 |
| Předmět: |
Digital electronics
Engineering AND-OR-Invert Pass transistor logic business.industry lcsh:Electronics Logic family lcsh:TK7800-8360 NOR logic ternary gates ternary logic Logic synthesis Logic gate Electronic engineering Hardware_INTEGRATEDCIRCUITS Hardware_ARITHMETICANDLOGICSTRUCTURES Three-input universal logic gate business multi valued logic mifgmos transistor Hardware_LOGICDESIGN |
| Zdroj: | ICTACT Journal on Microelectronics, Vol 1, Iss 2, Pp 45-56 (2015) |
| ISSN: | 2395-1680 2395-1672 |
| Popis: | Multi Valued Logic [MVL] has experienced major evolution in the recent past due to several advantages offered by them over the binary logic. Ternary Logic (a logic with radix 3 i.e. 3 logic states) is a promising alternative to the binary logic making it a thrust area of research. With the recent technological advancements, commercial realization of ternary circuits is watched with keen interests thereby attracting the attention of wide community of researchers to explore the usability of various alternative devices for implementing ternary circuits. This research proposes a novel hybrid approach based on combination of MIFGMOS (Multi Input Floating Gate Metal Oxide Semiconductor) transistor and conventional MOSFET for the realization of the ternary gates. In a digital system, NOT, NAND and NOR are of more importance as they are the building blocks of many other complex logic and arithmetic circuits. In this paper, the designs (based on hybrid combination of devices) of two input TNAND and TNOR gates are detailed which along with MIFGMOS transistor based T-inverter are further used to design TAND, TOR, TXOR and TXNOR gates. An extensive simulation of all the designed gates is carried out using TSPICE circuit simulator. The results demonstrate expected functionality of the proposed hybrid gates and additionally signify improvement in the performance parameters. The proposed hybrid approach combines the virtues of both the devices which facilitate the significant reduction in the circuit element count of the ternary gates as compared to earlier reported methods. |
| Databáze: | OpenAIRE |
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