Toward 100 Mega-Frames per Second: Design of an Ultimate Ultra-High-Speed Image Sensor
| Autor: | Junichi Nakai, Takeharu Etoh, Vo Le Cuong, Kohsei Takehara, Vu Truong Son Dao, Masatoshi Tanaka, Kenji Nishi, H. D. Nguyen, Toshiro Akino, Hitoshi Aoki |
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| Jazyk: | angličtina |
| Rok vydání: | 2009 |
| Předmět: |
backside illumination
Engineering Transducers ComputingMethodologies_IMAGEPROCESSINGANDCOMPUTERVISION Review RC time constant high sensitivity lcsh:Chemical technology Biochemistry Signal Analytical Chemistry Optics Back-illuminated sensor Photography lcsh:TP1-1185 Electrical and Electronic Engineering Image sensor Instrumentation Image resolution CCD image sensor Pixel business.industry Signal Processing Computer-Assisted ISIS Equipment Design Frame rate Image Enhancement Atomic and Molecular Physics and Optics Equipment Failure Analysis Transducer high speed business |
| Zdroj: | Sensors, Vol 10, Iss 1, Pp 16-35 (2009) Sensors (Basel, Switzerland) |
| ISSN: | 1424-8220 |
| Popis: | Our experience in the design of an ultra-high speed image sensor targeting the theoretical maximum frame rate is summarized. The imager is the backside illuminated in situ storage image sensor (BSI ISIS). It is confirmed that the critical factor limiting the highest frame rate is the signal electron transit time from the generation layer at the back side of each pixel to the input gate to the in situ storage area on the front side. The theoretical maximum frame rate is estimated at 100 Mega-frames per second (Mfps) by transient simulation study. The sensor has a spatial resolution of 140,800 pixels with 126 linear storage elements installed in each pixel. The very high sensitivity is ensured by application of backside illumination technology and cooling. The ultra-high frame rate is achieved by the in situ storage image sensor (ISIS) structure on the front side. In this paper, we summarize technologies developed to achieve the theoretical maximum frame rate, including: (1) a special p-well design by triple injections to generate a smooth electric field backside towards the collection gate on the front side, resulting in much shorter electron transit time; (2) design technique to reduce RC delay by employing an extra metal layer exclusively to electrodes responsible for ultra-high speed image capturing; (3) a CCD specific complementary on-chip inductance minimization technique with a couple of stacked differential bus lines. |
| Databáze: | OpenAIRE |
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