14-bit 2.2-MS/s sigma-delta ADC's
| Autor: | J. Perry, Masao Nakaya, Harufusa Kondoh, James C. Morizio, T. Kocak, G. Lynch, M. Hood, C. Geddie, M. Ishiwaki, Hideyuki Noda, T. Okuda, Takahiro Miki, Toshio Kumamoto, S. Madhavapeddi, C. Hughes, I.M. Hoke |
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| Rok vydání: | 2000 |
| Předmět: |
switched-capacitor circuits
Engineering business.industry Electrical engineering sigma–delta modulators Successive approximation ADC Topology (electrical circuits) cascaded ADC architectures Dissipation Switched capacitor Delta-sigma modulation hybrid AD converters CMOS Cascade Electronic engineering analogue circuits Oversampling mash ADC architectures Electrical and Electronic Engineering business |
| Zdroj: | Morizio, J, Hoke, M, Kocak, T & Geddie, C E A 2000, ' 14-bit 2.2-MS/s sigma-delta ADC's ', IEEE Journal of Solid-State Circuits, vol. 35, no. 7, pp. 968-976 . https://doi.org/10.1109/4.848205 |
| ISSN: | 1558-173X 0018-9200 |
| Popis: | This paper presents the design and test results of a fourth-order and sixth-order 14-bit 2.2-MS/s sigma-delta analog-to-digital converter (ADC). The analog modulator and digital decimator sections were implemented in a 0.35 /spl mu/m CMOS double-poly triple-level metal 3.3-V process. The design objective for these ADC's was to achieve 85 dB signal-to-noise distortion ratio (SNDR) with less than 200 mW power dissipation. Both modulators employ a cascade sigma-delta topology. The fourth-order modulator consists of two cascaded second-order stages which include 1-bit and 5-bit quantizers, respectively. The sixth-order modulator has a 2-2-2 cascade structure and 1-bit quantizer at the end of each stage. An oversampling ratio of 24 was selected to give the best SNDR and power consumption with realizable gain-matching requirements between the analog and digital sections. |
| Databáze: | OpenAIRE |
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