Investigation on threshold voltage instability under sweeping and DC gate bias stressing of SiC symmetrical and asymmetrical double-trench MOSFETs
| Autor: | J. Yang, S. Jahdi, B. Stark, J. Ortiz-Gonzalez, R. Wu, O. Alatise, P. Mellor |
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| Jazyk: | angličtina |
| Rok vydání: | 2022 |
| Zdroj: | Yang, J, Jahdi, S, Stark, B H, Ortiz-Gonzalez, J, Wu, R, Alatise, O & Mellor, P H 2022, Investigation on threshold voltage instability under sweeping and DC gate bias stressing of SiC symmetrical and asymmetrical double-trench MOSFETs . in 11th International Conference on Power Electronics, Machines and Drives (PEMD 2022) . Institution of Engineering and Technology (IET), Newcastle, UK, pp. 301-307, 11th International Conference on Power Electronics, Machines and Drives (PEMD 2022), Newcastle, United Kingdom, 21/06/22 . https://doi.org/10.1049/icp.2022.1066 |
| DOI: | 10.1049/icp.2022.1066 |
| Popis: | In this paper, measurements on gate threshold voltage drift by sweeping the gate voltage and both with positive and negative DC gate stressing are performed on symmetrical and asymmetrical double-trench SiC MOSFETs with comparison to SiC planar MOSFET at a range of temperatures. For the sweeping stress, the impact of sweeping speed on SiC MOSFET characteristics is also presented. In the experiments of DC gate stressing, the mobility degradation and threshold voltage drift values are obtained. Comparisons for threshold voltage drift in regard to temperature rise is made between different gate-structured SiC MOSFETs. |
| Databáze: | OpenAIRE |
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