A XOR-based associative memory block in 28 nm CMOS for interdisciplinary applications
| Autor: | Federico Fary, Pierluigi Luciano, Nicolo Vladi Biesuz, Calliope Louisa Sotiropoulou, Alberto Annovi, Alberto Stabile, Luca Frontini, Matteo M. Beretta, Marcello De Matteis, Francesco Crescioli, Valentino Liberali, A. Pezzotta, Seyed Ruhollah Shojaii, Andrea Baschirotto, Saverio Citraro, Fabrizio Palla, Paola Giannetti |
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| Přispěvatelé: | Annovi, A, Baschirotto, A, Beretta, M, Biesuz, N, Citraro, S, Crescioli, F, DE MATTEIS, M, Fary, F, Frontini, L, Giannetti, P, Liberali, V, Luciano, P, Palla, F, Pezzotta, A, Shojaii, S, Sotiropoulou, C, Stabile, A |
| Jazyk: | angličtina |
| Rok vydání: | 2016 |
| Předmět: |
Proposed architecture
AND-OR-Invert Pass transistor logic Least significant bit Computer science Parallel computing Static random access storage Associative storage High energy physic Pattern recognition XOR logic gate Track recognition High energy physics experiment CMOS integrated circuit Sequential logic Sense amplifier business.industry Associative processing Associative memory Logic family Medical application Image recognition Logic gate Computer circuits Reconfigurable hardware Memory operation Medical imaging business Combinational logic XOR gate Computer hardware Memory architecture Hardware_LOGICDESIGN NOR gate |
| Zdroj: | ICECS |
| Popis: | In this paper we describe a Content Addressable Memory architecture designed in 28 nm CMOS technology and based on the 65 nm XORAM cell previously developed. The cell is composed by two main blocks: a 6T SRAM, and a 4T XOR logic gate. Each XORAM cell makes a bitwise comparison between input data and stored data. The memory is organized in 18-bit words, and all the 18 XOR outputs bits must have a low logic value to trigger a high logic value of the single bit match line. A 18-input NOR gate performs this operation. The memory operation is triggered by the change of the least significant bit of the 18-bit input word, which is delayed w.r.t. the other bits. In this way, the logic does not require any clock. The proposed architecture is based on CMOS combinational logic, and it does not require any precharge operation, nor control and timing logic. The Associative Memory block is useful for several pattern recognition tasks, such as track recognition in high energy physics experiments, and image recognition for medical applications. |
| Databáze: | OpenAIRE |
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