| Autor: |
Peng Zhao, Hong Yu Li, Yu Dian Lim, Wen Wei Seit, Luca Guidoni, Chuan Seng Tan |
| Přispěvatelé: |
School of Electrical and Electronic Engineering, 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) |
| Jazyk: |
angličtina |
| Rok vydání: |
2022 |
| Předmět: |
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| Popis: |
In this work, we demonstrate the addition of grounding plane into the through silicon via (TSV) integrated ion trap to minimize the ion trap heating by effectively shielding the lossy silicon substrate from RF penetration. Windows are made onto this grounding plane to allow the passing through of the TSV. CMOS back-end-of-line process on 12-inch wafer platform is used for the trap fabrication. Upon the integration of grounding plane, the on-chip insertion loss is reduced to 0.06 dB (at RF frequency of 50 MHz). Based on the finite element modelling results, for trap with additional grounding plane, the Joule heating-induced temperature rise is reduced from >15 K to 2 K. This work demonstrates the compatibility of grounding plane and TSV in the application of scalable ion trap, enriching the integration toolbox for large scale ion trapping devices. National Research Foundation (NRF) This work is supported by the National Research Foundation, Singapore, under its ANR-NRF Joint Grant Call (NRF2020-NRF-ANR037 HIT). |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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