Energy Efficiency Features of the Intel Skylake-SP Processor and Their Impact on Performance
| Autor: | Andreas Gocht, Daniel Hackenberg, Robert Schöne, Mario Bielert, Thomas Ilsche |
|---|---|
| Jazyk: | angličtina |
| Rok vydání: | 2019 |
| Předmět: |
FOS: Computer and information sciences
business.industry Computer science 020209 energy 02 engineering and technology Systems modeling 512-bit Supercomputer Dynamic voltage scaling Uncore Computer Science - Distributed Parallel and Cluster Computing Embedded system 0202 electrical engineering electronic engineering information engineering x86 Distributed Parallel and Cluster Computing (cs.DC) Latency (engineering) business Efficient energy use |
| Zdroj: | HPCS |
| Popis: | The overwhelming majority of High Performance Computing (HPC) systems and server infrastructure uses Intel x86 processors. This makes an architectural analysis of these processors relevant for a wide audience of administrators and performance engineers. In this paper, we describe the effects of hardware controlled energy efficiency features for the Intel Skylake-SP processor. Due to the prolonged micro-architecture cycles, which extend the previous Tick-Tock scheme by Intel, our findings will also be relevant for succeeding architectures. The findings of this paper include the following: C-state latencies increased significantly over the Haswell-EP processor generation. The mechanism that controls the uncore frequency has a latency of approximately 10 ms and it is not possible to truly fix the uncore frequency to a specific level. The out-of-order throttling for workloads using 512 bit wide vectors also occurs at low processor frequencies. Data has a significant impact on processor power consumption which causes a large error in energy models relying only on instructions. 8 pages, HPCS2019, HPBench, READEX, HAEC, Horizon2020, H2020 grant agreement number 671657, DFG, CRC 912 |
| Databáze: | OpenAIRE |
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