Effects of JFET Region Design and Gate Oxide Thickness on the Static and Dynamic Performance of 650 V SiC Planar Power MOSFETs

Autor: Shengnan Zhu, Tianshi Liu, Junchong Fan, Hema Lata Rao Maddi, Marvin H. White, Anant K. Agarwal
Rok vydání: 2022
Předmět:
Zdroj: Materials; Volume 15; Issue 17; Pages: 5995
ISSN: 1996-1944
DOI: 10.3390/ma15175995
Popis: 650 V SiC planar MOSFETs with various JFET widths, JFET doping concentrations, and gate oxide thicknesses were fabricated by a commercial SiC foundry on two six-inch SiC epitaxial wafers. An orthogonal P+ layout was used for the 650 V SiC MOSFETs to reduce the ON-resistance. The devices were packaged into open-cavity TO-247 packages for evaluation. Trade-off analysis of the static and dynamic performance of the 650 V SiC power MOSFETs was conducted. The measurement results show that a short JFET region with an enhanced JFET doping concentration reduces specific ON-resistance (Ron,sp) and lowers the gate-drain capacitance (Cgd). It was experimentally shown that a thinner gate oxide further reduces Ron,sp, although with a penalty in terms of increased Cgd. A design with 0.5 μm half JFET width, enhanced JFET doping concentration of 5.5×1016 cm−3, and thin gate oxide produces an excellent high-frequency figure of merit (HF-FOM) among recently published studies on 650 V SiC devices.
Databáze: OpenAIRE
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