A Fully Programmable eFPGA-Augmented SoC for Smart Power Applications
| Autor: | Claudio Mucci, Davide Rossi, Francesco Renzini, Eleonora Franchi Scarselli, Roberto Canegallo |
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| Přispěvatelé: | Renzini, Francesco, Mucci, Claudio, Rossi, Davide, Franchi Scarselli, Eleonora, Canegallo, Roberto |
| Jazyk: | angličtina |
| Předmět: |
Embedded FPGA
microcontroller SoC smart-power business.industry Computer science 020208 electrical & electronic engineering Transistor Overhead (engineering) 02 engineering and technology Energy consumption 7. Clean energy law.invention Microcontroller CMOS law Embedded system 0202 electrical engineering electronic engineering information engineering System on a chip Electrical and Electronic Engineering business Field-programmable gate array Digital signal processing |
| Zdroj: | IEEE Transactions on Circuits and Systems I: Regular Papers |
| ISSN: | 1558-0806 1549-8328 |
| DOI: | 10.1109/tcsi.2019.2930412 |
| Popis: | This paper proposes a reconfigurable system on chip (SoC) for smart power applications. The system is composed of an ultra-low-power microcontroller for standard software programmability, coupled to an embedded-FPGA (eFPGA) to perform control-driven applications and lightweight digital signal processing, at lower power consumption and higher responsiveness than with processor-based execution. To the best of our knowledge, this is the first heterogeneous reconfigurable SoC targeting smart power applications. The SoC targets BCD technologies integrating bipolar, CMOS, and DMOS devices, typically featuring a small number of metal layers when compared with the traditional CMOS technologies. The added value of the proposed system is that the digital system is fully synthesizable since the eFPGA is based on a soft-core approach. This paper presents the results of integrating an eFPGA with a computational capability of $\simeq 1\text{k}$ equivalent gates in STMicroelectronics 90-nm BCD technology featuring five metal layers and high- $k$ transistors. We benchmarked our architecture on a wide range of applications relevant to the smart power domain. eFPGA integration in SoCs introduces a 20%–27% area overhead but has a straightforward benefit in terms of energy consumption, which proves reduction from about $10\times $ to $800\times $ . In terms of latency, the eFPGA implementation allows a gain from $8\times $ to $145\times $ comparing the pure cycles count. |
| Databáze: | OpenAIRE |
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