VLSI Implementation of a Scalable Pipeline MMSE MIMO Detector for a 4 x 4 MIMO-OFDM Receiver
| Autor: | Yoshikazu Miyanaga, Hirokazu Ikeuchi, Shingo Yoshizawa |
|---|---|
| Jazyk: | angličtina |
| Rok vydání: | 2011 |
| Předmět: |
3G MIMO
Computer science Orthogonal frequency-division multiplexing Applied Mathematics Pipeline (computing) ComputerSystemsOrganization_COMPUTER-COMMUNICATIONNETWORKS Detector Real-time computing MIMO Data_CODINGANDINFORMATIONTHEORY MIMO-OFDM Computer Graphics and Computer-Aided Design Multi-user MIMO MMSE Subcarrier MIMO detection wireless communications Signal Processing Electronic engineering Electrical and Electronic Engineering Computer Science::Information Theory |
| Zdroj: | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. (1):324-331 |
| ISSN: | 0916-8508 |
| Popis: | MIMO-OFDM performs signal detection on a subcarrier basis which requires high speed computation in MIMO detection due to its large computational cost. Conventional designs in a MIMO detector increase processing time in proportion to the number of subcarriers and have difficulty in real-time processing for large numbers of subcarriers. A complete pipeline MMSE MIMO detector presented in our previous work can provide high speed computation. However, it tends to be excessive in a circuit scale for small numbers of subcarriers. We propose a new scalable architecture to reduce circuit scale by adjusting the number of iterative operations according to various types of OFDM system. The proposed detector has reduced circuit area to about 1/2 to 1/7 in the previous design with providing acceptable latency time. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|