| Autor: |
Jing Kang, Fei Liu, Ya Hai, Yongshan Wang |
| Rok vydání: |
2023 |
| Předmět: |
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| Zdroj: |
Electronics; Volume 12; Issue 7; Pages: 1610 |
| ISSN: |
2079-9292 |
| DOI: |
10.3390/electronics12071610 |
| Popis: |
A four-phase all-digital delay-locked loop (ADDLL) with a de-skew circuit for NAND Flash high-speed interfaces is proposed. The proposed de-skew circuit adopts a fall-edge-judgment phase adjuster and a three-stage digitally controlled delay line to align the system input clock and 0∘ output clock of the four-phase DLL over a wide frequency range, thus solving the four-phase offset caused by clock skew. A parallel-cascade configuration is proposed to solve the variable phase alignment problem caused by mode switching, thus effectively improving the phase-locked accuracy. The proposed circuit is fabricated in the 0.13 μm CMOS process with a 0.072 mm2 core area. The chip testing results show an operating frequency range from 26 MHz to 1.55 GHz and a typical alignment error of approximately 17 ps. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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