Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs
| Autor: | Tovletoglou, Konstantinos, Mukhanov, Lev, Karakonstantis, Georgios, Chatzidimitriou, Athanasios, Papadimitriou, George, Kaliorakis, Manolis, Gizopoulos, Dimitris, Hadjilambrou, Zacharias, Sazeides, Yiannakis, Lampropulos, Alejandro, Das, Shidhartha, Vo, Phong |
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| Přispěvatelé: | Tovletoglou, Konstantinos [0000-0002-1513-3143] |
| Jazyk: | angličtina |
| Rok vydání: | 2018 |
| Předmět: |
010302 applied physics
Multi-core processor business.industry Computer science Error mitigation 02 engineering and technology Chip 01 natural sciences 020202 computer hardware & architecture Measurement study Embedded system 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Central processing unit business Energy (signal processing) Dram Voltage |
| Zdroj: | Tovletoglou, K, Mukhanov, L, Karakonstantis, G, Chatzidimitriou, A, Papadimitriou, G, Kaliorakis, M, Gizopoulos, D, Hadjilambrou, Z, Sazeides, Y, Lampropoulos, A, Das, S & Vo, P 2018, Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs . in 2018 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN): Proceedings . pp. 6-9, IEEE/IFIP International Conference on Dependable Systems and Networks, Luxembourg, Luxembourg, 25/06/2018 . https://doi.org/10.1109/DSN-W.2018.00013 DSN Workshops 2018 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W) |
| DOI: | 10.1109/DSN-W.2018.00013 |
| Popis: | In this paper, we present the results of our comprehensive measurement study of the timing and voltage guardbands in memories and cores of a commodity ARMv8 based micro-server. Using various synthetic micro-benchmarks, we reveal how the adopted voltage margins vary among the 8 cores of the CPU chip, and among 3 different sigma chips and we show how prone they are to worst-case voltage noise. In addition, we characterize the variation of 'weak' DRAM cells in terms of their retention time across 72 DRAM chips and evaluate the error mitigation efficacy of the available error-correcting codes in case of operation under aggressively relaxed refresh periods. Finally, we show the overall energy savings that could be achieved by shaving the adopted guardbands in the cores and memories using various applications. Our characterization results show the potential to obtain up-to 38.8% energy savings in cores and up-to 27.3% within DRAMs. 6 9 |
| Databáze: | OpenAIRE |
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