A survey of NoC evaluation platforms on FPGAs
| Autor: | Frederic Rousseau, Weslley N. Costa, Virginie Fresse, Otavio Alcantara de Lima |
|---|---|
| Přispěvatelé: | Laboratorio de Sistemas Digitais (IFCE), Laboratoire Hubert Curien [Saint Etienne] (LHC), Université Jean Monnet [Saint-Étienne] (UJM)-Centre National de la Recherche Scientifique (CNRS)-Institut d'Optique Graduate School (IOGS), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Funding for this project was provided by a grant fromla Region Rhˆone-Alpes as well as by the CNPq (process245340/2012-2)., Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]) |
| Jazyk: | angličtina |
| Rok vydání: | 2016 |
| Předmět: |
Network architecture
Emulation Class (computer programming) Computer science Interface (Java) business.industry 020208 electrical & electronic engineering emulation platform 02 engineering and technology Hardware_PERFORMANCEANDRELIABILITY 020202 computer hardware & architecture Software Computer architecture Embedded system 0202 electrical engineering electronic engineering information engineering Hardware_INTEGRATEDCIRCUITS [INFO.INFO-ES]Computer Science [cs]/Embedded Systems Field-programmable gate array business Traffic generation model Host (network) NoC FPGA |
| Zdroj: | The 2016 International Conference on Field-Programmable Technology The 2016 International Conference on Field-Programmable Technology, Dec 2016, Xian, China FPT |
| Popis: | Networks-on-chip (NoCs) have become a de facto communication standard for many core systems-on-chip (SoCs). A NoC has large design space composed of several parameters such as routing algorithm, task mapping, among others. SoC designers deeply rely on automatic evaluation tools in order to deal with the complexity of NoC design. An important class of NoCs evaluation tools are the platforms based on FPGAs, which improve the evaluation time and precision when compared to other solutions. There are different architectures of FPGA-based NoC evaluation tools. Details are scattered among several papers, making a comparative analysis hard to accomplish. This paper presents a comprehensive overview of FPGA tools for NoC evaluation. Our analysis covers aspects like network architecture, traffic generation and interface to the host PC. This provides insight on the platforms and their usefulness for different NoC evaluation tasks. |
| Databáze: | OpenAIRE |
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